Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O (input/output) count and area array solder bumps on the silicon chips to the base ceramic chip carriers, for example alumina carriers. The solder bump, typically a lead/tin alloy such as 95 Pb/5 Sn alloy, or a lead/indium alloy, such as 50 Pb/50 In, provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor chips to a carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the conductors on the chip carrier. The integrated circuit chip and the chip carrier are brought into contact and heated, e.g., by radiant heating, heated nitrogen, or heated inert gas, to cause the solder bump to reflow and form a solder column. This heating is typically to about 370 degrees Centigrade for about 3 minutes for Pb/Sn solders and to about 265 degrees Centigrade for about 3 minutes for Pb/In solders.
More recently, organic substrates have been developed. These organic substrates demand lower temperatures then ceramic chip carriers. The temperatures heretofore utilized with ceramic chip carriers cause severe thermal stresses or even resin deterioration in organic substrates. Thus, a need exists for solder compositions and techniques that avoid the temperatures heretofore associated with Pb/Sn solder alloys and ceramic chip carriers.